/* Copyright (c) 2025 Beijing Semidrive Technology Corporation
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
/** **************************************************************************************
 *  \file     Spi_Cfg.h
 *  \brief    This file contains interface header for CAN MCAL driver
 *
 * <table>
 * <tr><th>Date           <th>Version
 * <tr><td>2025-04-17 12:17:59     <td>1.0.0 R
 * </table>
 *****************************************************************************************/
#ifndef SPI_CFG_H
#define SPI_CFG_H
#include "Part.h"
#ifdef __cplusplus
extern "C" {
#endif
/*****************************************************************************************
 *                   Global Macro definition
 *****************************************************************************************/
/** \brief AuToSar Version of the SpiDriver*/
#define SPI_AR_RELEASE_MAJOR_VERSION 4U
#define SPI_AR_RELEASE_MINOR_VERSION 3U
#define SPI_AR_RELEASE_REVISION_VERSION 1U
/** \brief SoftWare version of the SpiDriver*/
#define SPI_SW_MAJOR_VERSION  3U
#define SPI_SW_MINOR_VERSION  1U
#define SPI_SW_PATCH_VERSION  0U

/** \brief Instance ID of the SPI SpiDriver*/
#define SPI_INSTANCE_ID 0U

#define SPI_VENDOR_ID 0x8C
#define SPI_MODULE_ID 83U

/** \brief Spi module levels */
#define SPI_LEVEL_0 0u
#define SPI_LEVEL_1 1u
#define SPI_LEVEL_2 2u

/** \brief  Number of Spi Drivers configured */
#define SPI_TOTAL_DRIVERS       1U
/** \brief  Total Number of Core  Supported */
#define SPI_CFG_CORE_NUM_MAX   (CPU_MAX_CORE_NUMBER)
/** \brief  Total Number of HW units configured */
/** Traceability       : SWSR_SPI_033 */
#define SPI_TOTAL_HW_COUNT      14U
/** \brief  Total Number of SpiChannel configured */
#define SPI_TOTAL_CH_COUNT	2U
/** \brief  Total Number of SpiJob configured */
#define SPI_TOTAL_JOB_COUNT	2U
/** \brief  Total  Number of SpiSequence configured */
#define SPI_TOTAL_SEQ_COUNT	2U
/** \brief  Total  Number of device configured */
#define SPI_TOTAL_DEV_COUNT	SPI_TOTAL_JOB_COUNT

#define SPI_MAX_CHANNEL     SPI_TOTAL_CH_COUNT
#define SPI_MAX_JOB         SPI_TOTAL_JOB_COUNT
#define SPI_MAX_SEQUENCE    SPI_TOTAL_SEQ_COUNT

/** \brief  Reference to configured DEM event to report "Hardware failure".
 * If the reference is not configured the error shall not be reported.*/
#define SPI_E_HARDWARE_ERROR (STD_OFF)
/** \brief  Dma enable or not */

#define SPI_ENABLE_DMA  STD_OFF
/** \brief  IB buffer align size */
#define SPI_BUFF_ALIGN_LEN      (CACHE_SIZE)
/** \brief  IB buffer size roundup size */
#define BUFF_SIZE_ROUNDUP_LEN   (CACHE_SIZE)
/** \brief  Switches the Spi_Cancel function ON or OFF.*/
#define	SPI_CANCEL_API	(STD_OFF)
/** \brief  Specifies whether concurrent Spi_SyncTransmit() is supported */
#define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT  (STD_OFF)
/** \brief  Selects the SPI Handler/Driver Channel Buffers usage allowed and delivered.
*           IB = 0; EB = 1; IB/EB = 2;*/
#define SPI_CHANNEL_BUFFERS_ALLOWED 0x1U

/** \brief  Switches the development error detection and notification on or off. */
#define SPI_DEV_ERROR_DETECT  (STD_OFF)
/** \brief Switches the Function Safety check and notification on or off. */
#define SPI_SAFETY_ENABLE  (STD_OFF)

/** \brief  Switches the Spi_GetHWUnitStatus function ON or OFF. */
#define SPI_HW_STATUS_API  (STD_OFF)

/** \brief  Switches the Interruptible Sequences handling functionality ON or OFF. */
#define SPI_INTERRUPTIBLE_SEQ_ALLOWED  (STD_OFF)

/** \brief  Selects the SPI Handler/Driver level of scalable functionality that is available and delivered. */
#define SPI_LEVEL_DELIVERED SPI_LEVEL_0

/** \brief  Configuration: SPI_VERSION_INFO_API
- if STD_ON, Function Spi_GetVersionInfo is available
- if STD_OFF,Function Spi_GetVersionInfo is not available
*/
#define SPI_VERSION_INFO_API	(STD_OFF)
/** \brief  Configuration: SPI_NO_CACHEABLE_NEEDED
- if STD_ON, Spi driver will not include dcache maintain code.
- if STD_OFF,Spi driver will include dcache maintain code.
*/
#define SPI_NO_CACHEABLE_NEEDED	(STD_OFF)

/** \brief   ResourceManager bot has spi configurations,default enable core0 */
#define SPI_CFG_ENABLE_CORE0 STD_ON
/** \brief  core1 is not enable spi */
#define SPI_CFG_ENABLE_CORE1 STD_OFF
/** \brief  core2 is not enable spi */
#define SPI_CFG_ENABLE_CORE2 STD_OFF
/** \brief  core3 is not enable spi */
#define SPI_CFG_ENABLE_CORE3 STD_OFF
/** \brief  core4 is not enable spi */
#define SPI_CFG_ENABLE_CORE4 STD_OFF
/** \brief  Handle for configured SpiChannel */
#define SpiConf_SpiChannel_SpiChannel_0  ((Spi_ChannelType)0U)
#define SpiConf_SpiChannel_SpiChannel_1  ((Spi_ChannelType)1U)


/** \brief  Handle for configured SpiJob */
#define SpiConf_SpiJob_SpiJob_0  ((Spi_JobType)0U)
#define SpiConf_SpiJob_SpiJob_1  ((Spi_JobType)1U)

/** \brief  Handle for configured SpiSequence */
#define SpiConf_SpiSequence_SpiSequence_0  ((Spi_SequenceType)0U)
#define SpiConf_SpiSequence_SpiSequence_1  ((Spi_SequenceType)1U)


/** \brief  Handles for external  HW unit USED  */
#define CSIB1 ((Spi_HWUnitType)0U)
#define CSIB2 ((Spi_HWUnitType)1U)
#define CSIB3 ((Spi_HWUnitType)2U)
#define CSIB4 ((Spi_HWUnitType)3U)
#define CSIB5 ((Spi_HWUnitType)4U)
#define CSIB6 ((Spi_HWUnitType)5U)
#define CSIB7 ((Spi_HWUnitType)6U)
#define CSIB8 ((Spi_HWUnitType)7U)
#define CSIB9 ((Spi_HWUnitType)8U)
#define CSIB10 ((Spi_HWUnitType)9U)
#define CSIB11 ((Spi_HWUnitType)10U)
#define CSIB12 ((Spi_HWUnitType)11U)
#define CSIB13 ((Spi_HWUnitType)12U)
#define CSIB14 ((Spi_HWUnitType)13U)
/** \brief  Handles for Chip Select(Slave select) allocated to the Job */
#define SPI_CS_0 (0U)
#define SPI_CS_1 (1U)
#define SPI_CS_2 (2U)
#define SPI_CS_3 (3U)
#define SPI_CS_4 (4U)
#define SPI_CS_5 (5U)


/** \brief  write buffers size*/
#define SPI_BUFFER_SIZE_CHANNEL_0  (10U)
#define SPI_BUFFER_SIZE_CHANNEL_1  (10U)

/** \brief  Switche to enable or disable Hardware loop back . */
#define SPI_HW_LOOPBACK  (STD_OFF)

#ifdef __cplusplus
}
#endif

#endif  /* SPI_CFG_H */

/* End of file */

